| Closing the Gap Between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design D Chinnery, K Keutzer Springer Science & Business Media, 2002 | 308 | 2002 |
| Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization D Nguyen, A Davare, M Orshansky, D Chinnery, B Thompson, K Keutzer International Symposium on Low Power Electronics and Design, 158-163, 2003 | 216 | 2003 |
| ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement IS Bustany, D Chinnery, JR Shinnerl, V Yutsis International Symposium on Physical Design, 157-164, 2015 | 159 | 2015 |
| Closing the gap between ASIC and custom: An ASIC perspective DG Chinnery, K Keutzer Design Automation Conference 37, 637-642, 2000 | 124 | 2000 |
| Linear programming for sizing, Vth and Vdd assignment DG Chinnery, K Keutzer International Symposium on Low Power Electronics and Design, 149-154, 2005 | 99 | 2005 |
| ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement V Yutsis, IS Bustany, D Chinnery, JR Shinnerl, WH Liu International Symposium on Physical Design, 161-168, 2014 | 76 | 2014 |
| Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design D Chinnery, K Keutzer Springer Science & Business Media, 2007 | 76 | 2007 |
| A functional validation technique: biased-random simulation guided by observability-based coverage S Tasiran, F Fallah, DG Chinnery, SJ Weber, K Keutzer International Conference on Computer Design, 82-88, 2001 | 63 | 2001 |
| Closing the Power Gap Between ASIC and Custom: an ASIC Perspective DG Chinnery, K Keutzer Design Automation Conference, 275-280, 2005 | 55 | 2005 |
| Low power multiplication algorithm for switching activity reduction through operand decomposition M Ito, D Chinnery, K Keutzer International Conference on Computer Design, 21-26, 2003 | 44 | 2003 |
| Achieving 550 MHz in an ASIC methodology DG Chinnery, B Nikolic, K Keutzer Design Automation Conference, 420-425, 2001 | 36 | 2001 |
| Automatic replacement of flip-flops by latches in ASICs D Chinnery, K Keutzer, J Sanghavi, E Killian, K Sheth Closing the Gap Between ASIC and Custom: Tools and Techniques for High …, 2002 | 23 | 2002 |
| Fast Lagrangian Relaxation based gate sizing using multi-threading A Sharma, D Chinnery, S Bhardwaj, C Chu International Conference on Computer-Aided Design, 426-433, 2015 | 22 | 2015 |
| Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations A Sharma, D Chinnery, T Reimann, S Bhardwaj, C Chu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 21 | 2020 |
| Reducing the timing overhead D Chinnery, K Keutzer Closing the Gap Between ASIC and Custom: Tools and Techniques for High …, 2002 | 18 | 2002 |
| Timing-Driven and Placement-Aware Multibit Register Composition I Seitanidis, G Dimitrakopoulos, PM Mattheakis, L Masse-Navette, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 15 | 2018 |
| Overview of the Factors Affecting the Power Consumption D Chinnery, K Keutzer Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low …, 2007 | 14 | 2007 |
| Low Power Design Automation DG Chinnery University of California, Berkeley, 2006 | 14 | 2006 |
| Rapid gate sizing with fewer iterations of lagrangian relaxation A Sharma, D Chinnery, S Dhamdhere, C Chu 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 337-343, 2017 | 13 | 2017 |
| High performance and low power design techniques for ASIC and custom in nanometer technologies D Chinnery International Symposium on Physical Design, 25-32, 2013 | 11 | 2013 |
Kurt KeutzerProfessor of the Graduate School, EECS, University of California, BerkeleyE-mailová adresa ověřena na: berkeley.edu
