| High-throughput ring-LWE cryptoprocessors CP Rentería-Mejía, J Velasco-Medina IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 62 | 2017 |
| Hardware design of an NTT-based polynomial multiplier CP Rentería-Mejía, J Velasco-Medina 2014 IX Southern Conference on Programmable Logic (SPL), 1-5, 2014 | 22 | 2014 |
| Hardware implementation of the Smith-Waterman algorithm using a systolic architecture JM Marmolejo-Tejada, V Trujillo-Olaya, CP Rentería-Mejía, ... 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 21 | 2014 |
| Design of an 8192-bit RSA cryptoprocessor based on systolic architecture CP Rentería-Mejía, V Trujillo-Olaya, J Velasco-Medina 2012 VIII Southern Conference on Programmable Logic, 1-6, 2012 | 10 | 2012 |
| Lattice-based cryptoprocessor for CCA-secure identity-based encryption CP Rentería-Mejía, J Velasco-Medina IEEE Transactions on Circuits and Systems I: Regular Papers 67 (7), 2331-2344, 2020 | 8 | 2020 |
| Hardware design of FFT polynomial multipliers CP Rentería-Mejía, A López-Parrado, J Velasco-Medina 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 6 | 2014 |
| 8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digit CP Rentería-Mejía, V Trujillo-Olaya, J Velasco-Medina 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 3 | 2013 |
| Diseño de un procesador multi-efecto para guitarra eléctrica basado en FPGAs. J Velasco Medina, PP Liévano Torres, JE Guerrero Ramírez, ... | | 2018 |
| DESIGN OF A PROGRAMMABLE MICROSYSTEM FOR DIGITAL AUDIO EFFECTS USING FPGAS JM Espinosa Durán, PP Liévano Torres, CP Rentería Mejía, ... Revista EIA, 133-146, 2014 | | 2014 |
| DISEÑO DE UN MICROSISTEMA PROGRAMABLE PARA EFECTOS DE AUDIO DIGITAL USANDO FPGAS. PP LIÉVANO TORRES, JM ESPINOSA DURÁN, CP RENTERÍA MEJÍA, ... Revista EIA 11 (22), 2014 | | 2014 |
| Diseño de un microsistema programable para efectos de audio digital usando fpgas JME Durán, PPL Torres, CPR Mejía, JV Medina Revista EIA 11 (22), 133-146, 2014 | | 2014 |
| Diseño de un criptoprocesador RSA de 8192 bits usando un arreglo sistólico CP Renteria Mejia | | 2012 |
| Hardware Design of an n-coefficient NTT-Based Polynomial Multiplier CP Rentería-Mejía, J Velasco-Medina | | |
Jaime Velasco MedinaUniversidad del ValleVerified email at correounivalle.edu.co
