| On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits KK Kim, W Wang, K Choi IEEE Transactions on Circuits and Systems II: Express Briefs 57 (10), 798-802, 2010 | 140 | 2010 |
| Area-efficient parallel FIR digital filter structures for symmetric convolutions based on fast FIR algorithm YC Tsao, K Choi IEEE transactions on very large scale integration (vlsi) systems 20 (2), 366-371, 2010 | 122 | 2010 |
| High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology H Nan, K Choi IEEE Transactions on Circuits and Systems I: Regular Papers 59 (7), 1445-1457, 2012 | 120 | 2012 |
| Area-efficient VLSI implementation for parallel linear-phase FIR digital filters of odd length based on fast FIR algorithm YC Tsao, K Choi IEEE Transactions on Circuits and Systems II: Express Briefs 59 (6), 371-375, 2012 | 74 | 2012 |
| A randomized, double-blind, multicenter, parallel group study to compare relative efficacies of the topical gels 3% erythromycin/5% benzoyl peroxide and 0.025% tretinoin … AK Gupta, CW Lynde, RAW Kunynetz, S Amin, K Choi, E Goldstein Journal of Cutaneous Medicine and Surgery: Incorporating Medical and …, 2003 | 61 | 2003 |
| Game theory-based security vulnerability quantification for social internet of things S Lee, S Kim, K Choi, T Shon Future Generation Computer Systems 82, 752-760, 2018 | 42 | 2018 |
| Low cost and highly reliable hardened latch design for nanoscale CMOS technology H Nan, K Choi Microelectronics Reliability 52 (6), 1209-1214, 2012 | 37 | 2012 |
| Hybrid CMOS and CNFET power gating in ultralow voltage design KK Kim, YB Kim, K Choi IEEE Transactions on Nanotechnology 10 (6), 1439-1448, 2011 | 36 | 2011 |
| Activity-driven fine-grained clock gating and run time power gating integration L Li, K Choi, H Nan IEEE transactions on very large scale integration (VLSI) systems 21 (8 …, 2012 | 29 | 2012 |
| Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes Y Zhang, Q Tong, L Li, W Wang, K Choi, JE Jang, H Jung, SY Ahn 2012 International SoC Design Conference (ISOCC), 21-24, 2012 | 25 | 2012 |
| Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously L Li, K Choi, H Nan 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 25 | 2011 |
| Ultralow-voltage power gating structure using low threshold voltage KK Kim, H Nan, K Choi IEEE Transactions on Circuits and Systems II: Express Briefs 56 (12), 926-930, 2009 | 25 | 2009 |
| Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology H Nan, K Choi Microelectronics Reliability 51 (12), 2086-2092, 2011 | 23 | 2011 |
| Novel ternary logic design based on CNFET H Nan, K Choi 2010 International SoC Design Conference, 115-118, 2010 | 22 | 2010 |
| Activity-driven optimised bus-specific-clock-gating for ultra-low-power smart space applications L Li, K Choi IET communications 5 (17), 2501-2508, 2011 | 18 | 2011 |
| A novel 9T SRAM design in sub-threshold region AR Ramani, K Choi 2011 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY, 1-6, 2011 | 18 | 2011 |
| SeSCG: selective sequential clock gating for ultra-low-power multimedia mobile processor design L Li, W Wang, K Choi, S Park, MK Chung 2010 IEEE International Conference on Electro/Information Technology, 1-6, 2010 | 17 | 2010 |
| Dynamic learning model update of hybrid-classifiers for intrusion detection J Cho, T Shon, K Choi, J Moon The Journal of Supercomputing 64, 522-526, 2013 | 15 | 2013 |
| Power dissipation and area comparison of 512-bit and 1024-bit key AES J Cho, S Soekamtoputra, K Choi, J Moon Computers & Mathematics with Applications 65 (9), 1378-1383, 2013 | 15 | 2013 |
| Hardware-efficient VLSI implementation for 3-parallel linear-phase FIR digital filter of odd length YC Tsao, K Choi 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 998-1001, 2012 | 15 | 2012 |
