The Complementary FET (CFET) for CMOS scaling beyond N3 J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ... 2018 IEEE Symposium on Vlsi Technology, 141-142, 2018 | 146 | 2018 |
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ... IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018 | 123 | 2018 |
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017 | 102 | 2017 |
Benchmarking of Standard-Cell Based Memories in the Sub- Domain in 65-nm CMOS Technology P Meinerzhagen, SMY Sherazi, A Burg, JN Rodrigues IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1 (2 …, 2011 | 98 | 2011 |
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ... 2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016 | 77 | 2016 |
The impact of sequential-3D integration on semiconductor scaling roadmap A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017 | 56 | 2017 |
A receiver architecture for devices in wireless body area networks H Sjoland, JB Anderson, C Bryant, R Chandra, O Edfors, AJ Johansson, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (1 …, 2012 | 55 | 2012 |
Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ... 2019 Symposium on VLSI Technology, T204-T205, 2019 | 44 | 2019 |
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells MG Bardon, Y Sherazi, D Jang, D Yakimets, P Schuddinck, R Baert, ... 2018 IEEE Symposium on VLSI Technology, 143-144, 2018 | 44 | 2018 |
Standard cell design in N7: EUV vs. immersion B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability IX, 9 (Proc …, 2015 | 41 | 2015 |
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ... 2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012 | 41 | 2012 |
DTCO at N7 and beyond: patterning and electrical compromises and opportunities J Ryckaert, P Raghavan, P Schuddinck, HB Trong, A Mallik, SS Sakhare, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427 (doi …, 2015 | 37 | 2015 |
DTCO exploration for efficient standard cell power rails B Chava, J Ryckaert, L Mattii, SMY Sherazi, P Debacker, A Spessot, ... Design-Process-Technology Co-optimization for Manufacturability XII 10588, 89-94, 2018 | 35 | 2018 |
Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet SMY Sherazi, M Cupak, P Weckx, O Zografos, D Jang, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 32 | 2019 |
Low track height standard cell design in iN7 using scaling boosters SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 32 | 2017 |
Impact of a SADP flow on the design and process for N10/N7 metal layers W Gillijns, SMY Sherazi, D Trivkovic, B Chava, B Vandewalle, V Gerousis, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427 (doi …, 2015 | 29 | 2015 |
Architectural strategies in standard-cell design for the 7 nm and beyond technology node SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507-013507, 2016 | 25 | 2016 |
Single exposure EUV patterning of BEOL metal layers on the IMEC iN7 platform VMB Carballo, J Bekaert, M Mao, BK Kotowska, S Larivière, I Ciofi, ... Extreme Ultraviolet (EUV) Lithography VIII 10143, 241-250, 2017 | 21 | 2017 |
CFET standard-cell design down to 3Track height for node 3nm and below SMY Sherazi, JK Chae, P Debacker, L Matti, D Verkest, A Mocuta, RH Kim, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 15 | 2019 |
Track height reduction for standard-cell in below 5nm node: how low can you go? SMY Sherazi, JK Chae, P Debacker, L Matti, P Raghavan, V Gerousis, ... Design-Process-Technology Co-optimization for Manufacturability XII 10588, 66-78, 2018 | 14 | 2018 |