| Material removal mechanism in chemical mechanical polishing: theory and modeling J Luo, DA Dornfeld IEEE transactions on semiconductor manufacturing 14 (2), 112-133, 2001 | 875 | 2001 |
| Dummy filling technique for improved planarization of chip surface topography S Sinha, J Luo, CC Chiang US Patent 7,509,622, 2009 | 239 | 2009 |
| Effects of abrasive size distribution in chemical mechanical planarization: modeling and verification J Luo, DA Dornfeld IEEE Transactions on Semiconductor Manufacturing 16 (3), 469-476, 2003 | 207 | 2003 |
| Analysis of two-dimensional thin structures (from micro-to nano-scales) using the boundary element method JF Luo, YJ Liu, EJ Berger Computational Mechanics 22 (5), 404-412, 1998 | 190 | 1998 |
| Material removal regions in chemical mechanical planarization for submicron integrated circuit fabrication: coupling effects of slurry chemicals, abrasive size distribution … J Luo, DA Dornfeld IEEE Transactions on Semiconductor Manufacturing 16 (1), 45-56, 2003 | 138 | 2003 |
| Modeling of interphases in fiber-reinforced composites under transverse loading using the boundary element method YJ Liu, N Xu, JF Luo J. Appl. Mech. 67 (1), 41-49, 2000 | 137 | 2000 |
| Integrated modeling of chemical mechanical planarization for sub-micron IC fabrication: from particle scale to feature, die and wafer scales J Luo, DA Dornfeld Springer Science & Business Media, 2004 | 113 | 2004 |
| Interfacial stress analysis for multi-coating systems using an advanced boundary element method JF Luo, YJ Liu, EJ Berger Computational Mechanics 24, 448-455, 2000 | 106 | 2000 |
| Simulating topography of a conductive material in a semiconductor wafer J Luo, Q Su, C Chiang US Patent 7,289,933, 2007 | 99 | 2007 |
| A comparative study of double-gate and surroundinggate MOSFETs in strong inversion and accumulation using an analytical model Y Chen, J Luo Integration 1 (2), 6, 2001 | 70 | 2001 |
| A layout dependent full-chip copper electroplating topography model J Luo, Q Su, C Chiang, J Kawa ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 47 | 2005 |
| An IC manufacturing yield model considering intra-die variations J Luo, S Sinha, Q Su, J Kawa, C Chiang Proceedings of the 43rd annual Design Automation Conference, 749-754, 2006 | 43 | 2006 |
| Model based layout pattern dependent metal filling algorithm for improved chip surface uniformity in the copper process S Sinha, J Luo, C Chiang 2007 Asia and South Pacific Design Automation Conference, 1-6, 2007 | 37 | 2007 |
| Optimization of CMP from the viewpoint of consumable effects J Luo, DA Dornfeld Journal of The Electrochemical Society 150 (12), G807, 2003 | 36 | 2003 |
| Predicting IC manufacturing yield by considering both systematic and random intra-die process variations J Luo, S Sinha, Q Su, CC Chiang US Patent 8,000,826, 2011 | 23 | 2011 |
| Integrated modeling of chemical mechanical planarization/polishing (CMP) for integrated circuit fabrication: from particle scale to die and wafer scales J Luo University of California, Berkeley, 2003 | 22 | 2003 |
| Routing analysis with double pattern lithography J Luo, G Chen US Patent 8,856,697, 2014 | 19 | 2014 |
| Integrated model for chemical-mechanical polishing based on a comprehensive material removal model J Luo, DA Dornfeld, Z Mao, E Hwang Sixth International Conference on Chemical-Mechanical Polish (CMP …, 2001 | 14 | 2001 |
| Impact of modern process technologies on the electrical parameters of interconnects D Sinha, J Luo, S Rajagopalan, S Batterywala, NV Shenoy, H Zhou 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 13 | 2007 |
| Circuit design including design rule violation correction utilizing patches based on deep reinforcement learning J Luo US Patent 10,755,026, 2020 | 12 | 2020 |
Charles ChiangSynopsysE-mailová adresa ověřena na: synopsys.com
