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Alberto Sangiovanni Vincentelli
Alberto Sangiovanni Vincentelli
Professor of EECS, University of California, Berkeley
E-mailová adresa ověřena na: eecs.berkeley.edu - Domovská stránka
Název
Citace
Citace
Rok
Logic minimization algorithms for VLSI synthesis
RK Brayton
Springer, 1984
27451984
SIS: A system for sequential circuit synthesis
ME Sentovich
Memorandom no. UCB/ERL M92/41, 1992
24811992
MIS: A multiple-level logic optimization system
RK Brayton, R Rudell, A Sangiovanni-Vincentelli, AR Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1987
16761987
System-level design: Orthogonalization of concerns and platform-based design
K Keutzer, AR Newton, JM Rabaey, A Sangiovanni-Vincentelli
IEEE transactions on computer-aided design of integrated circuits and …, 2000
13612000
Hardware-software co-design of embedded systems: the POLIS approach
F Balarin, P Giusto, A Jurecska, C Passerone, E Sentovich, B Tabbara, ...
Springer Science & Business Media, 2012
11442012
The waveform relaxation method for time-domain analysis of large scale integrated circuits
E Lelarasmee, AE Ruehli, AL Sangiovanni-Vincentelli
IEEE transactions on computer-aided design of integrated circuits and …, 1982
11171982
Modeling cyber–physical systems
P Derler, EA Lee, AS Vincentelli
Proceedings of the IEEE 100 (1), 13-28, 2011
10772011
VIS: A system for verification and synthesis
RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ...
Computer Aided Verification: 8th International Conference, CAV'96 New …, 1996
9801996
A framework for comparing models of computation
EA Lee, A Sangiovanni-Vincentelli
IEEE Transactions on computer-aided design of integrated circuits and …, 1998
9321998
Design of embedded systems: Formal models, validation, and synthesis
S Edwards, L Lavagno, EA Lee, A Sangiovanni-Vincentelli
Proceedings of the IEEE 85 (3), 366-390, 1997
8141997
The TimberWolf placement and routing package
C Sechen, A Sangiovanni-Vincentelli
IEEE Journal of Solid-State Circuits 20 (2), 510-522, 1985
7631985
Logic verification using binary decision diagrams in a logic synthesis environment
S Malik, AR Wang, RK Brayton, A Sangiovanni-Vincentelli
1988 IEEE International Conference on Computer-Aided Design, 6, 7, 8, 9-6, 7 …, 1988
7601988
Sequential circuit design using synthesis and optimization
EM Sentovich, KJ Singh, C Moon, H Savoj, RK Brayton, ...
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in …, 1992
7271992
Steady-state methods for simulating analog and microwave circuits
KS Kundert, JK White, AL Sangiovanni-Vincentelli
Springer Science & Business Media, 2013
7102013
Convergence and finite-time behavior of simulated annealing
D Mitra, F Romeo, A Sangiovanni-Vincentelli
Advances in applied probability 18 (3), 747-771, 1986
7071986
Metropolis: An integrated electronic system design environment
F Balarin, Y Watanabe, H Hsieh, L Lavagno, C Passerone, ...
Computer 36 (4), 45-52, 2003
6782003
Platform-based design and software design methodology for embedded systems
A Sangiovanni-Vincentelli, G Martin
IEEE Design & Test of Computers 18 (6), 23-33, 2001
6592001
Multilevel logic synthesis
RK Brayton, GD Hachtel, AL Sangiovanni-Vincentelli
Proceedings of the IEEE 78 (2), 264-300, 1990
6391990
Implicit state enumeration of finite state machines using BDD's
HJ Touati, H Savoj, B Lin, RK Brayton, A Sangiovanni-Vincentelli
1990 IEEE International Conference on Computer-Aided Design. Digest of …, 1990
5981990
Multiple-valued minimization for PLA optimization
RL Rudell, A Sangiovanni-Vincentelli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1987
5971987
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Články 1–20