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Ari Paasio
Ari Paasio
Partner, Kovilta Ltd.
Verified email at kovilta.fi
Title
Cited by
Cited by
Year
Reducing the feature vector length in local binary pattern based face recognition
O Lahdenoja, M Laiho, A Paasio
IEEE International Conference on Image Processing 2005 2, II-914, 2005
922005
Accelerometer-based method for extracting respiratory and cardiac gating information for dual gating during nuclear medicine imaging
M Jafari Tadi, T Koivisto, M Pänkäälä, A Paasio
International journal of biomedical imaging 2014, 2014
872014
MIPA4k: A 64× 64 cell mixed-mode image processor array
J Poikonen, M Laiho, A Paasio
2009 IEEE International Symposium on Circuits and Systems, 1927-1930, 2009
782009
Minimum size 0.5 micron CMOS programmable 48X48 CNN test chip
A Paasio
Proc. 1997 European Conffernce on Circuit theory and Design, 1997
701997
A qcif resolution binary i/o cnn-um chip
A Paasio, A Kananen, K Halonen, V Porra
Journal of VLSI signal processing systems for signal, image and video …, 1999
501999
Seismocardiography: Toward heart rate variability (HRV) estimation
MJ Tadi, E Lehtonen, T Koivisto, M Pänkäälä, A Paasio, M Teräs
2015 IEEE International Symposium on Medical Measurements and Applications …, 2015
402015
CNN template robustness with different output nonlinearities
A Paasio, A Dawidziuk
International Journal of Circuit Theory and Applications 27 (1), 87-102, 1999
341999
A 176 x 144 processor binary I/O CNN-UM chip design
A Paasio, A Kananen, V Porra
European Conference on Circuit Theory and Design ECCTD'99, Stresa, Italy …, 1999
341999
CNN applications from the hardware point of view: Video sequence segmentation
A Kananen, A Paasio, M Laiho, K Halonen
International journal of circuit theory and applications 30 (2‐3), 117-137, 2002
322002
A mixed‐mode polynomial‐type CNN for analysing brain electrical activity in epilepsy
M Laiho, A Paasio, A Kananen, K Halonen
International journal of circuit theory and applications 30 (2‐3), 165-180, 2002
272002
A new cell output nonlinearity for dense cellular nonlinear network integration
A Paasio, K Halonen
IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2001
272001
A massively parallel algorithm for local binary pattern based face recognition
O Lahdenoja, J Maunu, M Laiho, A Paasio
2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006
262006
Dedicated hardware for parallel extraction of local binary pattern feature vectors
M Laiho, O Lahdenoja, A Paasio
2005 9th international workshop on cellular neural networks and their …, 2005
252005
Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes
VM Brea, DL Vilariño, A Paasio, D Cabello
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (5), 997-1013, 2004
252004
A new algorithm for segmentation of cardiac quiescent phases and cardiac time intervals using seismocardiography
MJ Tadi, T Koivisto, M Pänkäälä, A Paasio, T Knuutila, M Teräs, ...
Sixth International Conference on Graphic and Image Processing (ICGIP 2014 …, 2015
242015
An analog array processor hardware realization with multiple new features
A Paasio, M Laiho, A Kananen, K Halonen
Proceedings of the 2002 International Joint Conference on Neural Networks …, 2002
232002
VLSI implementation of a binary CNN: First measurement results
J Flak, M Laiho, A Paasio, K Halonen
Proceedings of the 8th IEEE International Workshop on Cellular Neural …, 2004
222004
Dense CMOS implementation of a binary‐programmable cellular neural network
J Flak, M Laiho, A Paasio, K Halonen
International journal of circuit theory and applications 34 (4), 429-443, 2006
212006
Integration of Cellular Nonlinear Network Universal Machine.
AJ Paasio
212000
Template design for cellular nonlinear networks with 1-bit weights
M Laiho, A Paasio, J Flak, KAI Halonen
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (3), 904-913, 2008
202008
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