| High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH computer architecture news 38 (3), 60-71, 2010 | 1002 | 2010 |
| Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007 | 986 | 2007 |
| Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer ACM SIGARCH Computer Architecture News 40 (3), 213-224, 2012 | 450 | 2012 |
| Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008 | 424 | 2008 |
| Dramsim: a memory system simulator D Wang, B Ganesh, N Tuaycharoen, K Baynes, A Jaleel, B Jacob ACM SIGARCH Computer Architecture News 33 (4), 100-107, 2005 | 412 | 2005 |
| SHiP: Signature-based hit predictor for high performance caching CJ Wu, A Jaleel, W Hasenplaugh, M Martonosi, SC Steely Jr, J Emer Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 340 | 2011 |
| Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks L Domnitser, A Jaleel, J Loew, N Abu-Ghazaleh, D Ponomarev ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-21, 2012 | 313 | 2012 |
| Colt: Coalesced large-reach tlbs B Pham, V Vaidyanathan, A Jaleel, A Bhattacharjee 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 258-269, 2012 | 257 | 2012 |
| MCM-GPU: Multi-chip-module GPUs for continued performance scalability A Arunkumar, E Bolotin, B Cho, U Milic, E Ebrahimi, O Villa, A Jaleel, ... ACM SIGARCH Computer Architecture News 45 (2), 320-332, 2017 | 249 | 2017 |
| Extensor: An accelerator for sparse tensor algebra K Hegde, H Asghari-Moghaddam, M Pellauer, N Crago, A Jaleel, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 242 | 2019 |
| CMP $ im: A Pin-based on-the-fly multi-core cache simulator A Jaleel, RS Cohn, CK Luk, B Jacob Proceedings of the Fourth Annual Workshop on Modeling, Benchmarking and …, 2008 | 241 | 2008 |
| Biobench: A benchmark suite of bioinformatics applications K Albayraktaroglu, A Jaleel, X Wu, M Franklin, B Jacob, CW Tseng, ... IEEE International Symposium on Performance Analysis of Systems and Software …, 2005 | 229 | 2005 |
| Cameo: A two-level memory organization with capacity of main memory and flexibility of hardware-managed cache CC Chou, A Jaleel, MK Qureshi 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 1-12, 2014 | 201 | 2014 |
| Achieving non-inclusive cache performance with inclusive caches: Temporal locality aware (TLA) cache management policies A Jaleel, E Borch, M Bhandaru, SC Steely Jr, J Emer 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 151-162, 2010 | 193 | 2010 |
| Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads A Jaleel, M Mattina, B Jacob The Twelfth International Symposium on High-Performance Computer …, 2006 | 179 | 2006 |
| A high-resolution side-channel attack on last-level cache M Kayaalp, N Abu-Ghazaleh, D Ponomarev, A Jaleel Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 165 | 2016 |
| PACMan: prefetch-aware cache management for high performance caching CJ Wu, A Jaleel, M Martonosi, SC Steely Jr, J Emer Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 164 | 2011 |
| Triggered instructions: A control paradigm for spatially-programmed architectures A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ... ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013 | 161 | 2013 |
| Analyzing parallel programs with pin M Bach, M Charney, R Cohn, E Demikhovsky, T Devor, K Hazelwood, ... Computer 43 (3), 34-41, 2010 | 160 | 2010 |
| Memory characterization of workloads using instrumentation-driven simulation A Jaleel Web Copy: http://www. glue. umd. edu/ajaleel/workload, 1-12, 2010 | 151 | 2010 |
Joel EmerProfessor of the Practice, MIT - Sr. Distinguished Research Scientist, NvidiaVerified email at csail.mit.edu
