An integrated row-based cell placement and interconnect synthesis tool for large SFQ logic circuits SN Shahsavani, TR Lin, A Shafaei, CJ Fourie, M Pedram IEEE Transactions on Applied Superconductivity 27 (4), 1-8, 2017 | 87 | 2017 |
A heuristic machine learning-based algorithm for power and thermal management of heterogeneous MPSoCs A Iranfar, SN Shahsavani, M Kamal, A Afzali-Kusha 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 37 | 2015 |
A minimum-skew clock tree synthesis algorithm for single flux quantum logic circuits SN Shahsavani, M Pedram IEEE Transactions on Applied Superconductivity 29 (8), 1-13, 2019 | 33 | 2019 |
A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement SN Shahsavani, A Shafaei, M Pedram 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 28 | 2018 |
NullaNet Tiny: Ultra-low-latency DNN inference through fixed-function combinational logic M Nazemi, A Fayyazi, A Esmaili, A Khare, SN Shahsavani, M Pedram 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 17 | 2021 |
Sport lab sfq logic circuit benchmark suite N Katam, SN Shahsavani, TR Lin, G Pasandi, A Shafaei, M Pedram Univ. Southern California, Los Angeles, CA, USA, Tech. Rep, 2017 | 14 | 2017 |
Accurate Margin Calculation for Single Flux Quantum Logic Cells SN Shahsavani, B Zhang, M Pedram Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 10 | 2018 |
Margin and yield optimization of single flux quantum logic cells using swarm optimization techniques MA Karamuftuoglu, SN Shahsavani, M Pedram IEEE Transactions on Applied Superconductivity 33 (1), 1-10, 2022 | 8 | 2022 |
TDP-ADMM: A timing driven placement approach for superconductive electronic circuits using alternating direction method of multipliers SN Shahsavani, M Pedram 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 8 | 2020 |
A timing uncertainty-aware clock tree topology generation algorithm for single flux quantum circuits SN Shahsavani, B Zhang, M Pedram 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 278-281, 2020 | 5 | 2020 |
Margin Optimization of Single Flux Quantum Logic Cells MA Karamuftuoglu, S Nazar Shahsavani, M Pedram Design Automation of Quantum Computers, 105-133, 2022 | 3 | 2022 |
Efficient compilation and mapping of fixed function combinational logic onto digital signal processors targeting neural network inference and utilizing high-level synthesis SN Shahsavani, A Fayyazi, M Nazemi, M Pedram arXiv preprint arXiv:2208.00302, 2022 | 2 | 2022 |
A variation-aware hold time fixing methodology for single flux quantum logic circuits X Li, SN Shahsavani, X Zhou, M Pedram, PA Beerel ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (6 …, 2021 | 2 | 2021 |
A hyper-parameter based margin calculation algorithm for single flux quantum logic cells SN Shahsavani, M Pedram 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 645-650, 2019 | 2 | 2019 |
A thermally-aware energy minimization methodology for global interconnects SN Shahsavani, A Shafaei, S Nazarian, M Pedram Design, Automation & Test in Europe Conference & Exhibition (DATE) 2017 …, 2017 | 1 | 2017 |
A Clock Synthesis Algorithm for Hierarchical Chains of Homogeneous Clover-Leaves Clock Networks for Single Flux Quantum Logic Circuits SN Shahsavani, RN Tadros, PA Beerel, M Pedram 2019 IEEE International Superconductive Electronics Conference (ISEC), 1-3, 2019 | | 2019 |