| Novel dynamic state-deflection method for gate-level design obfuscation J Dofe, Q Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 95 | 2017 |
| Hardware security assurance in emerging IoT applications J Dofe, J Frey, Q Yu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2050-2053, 2016 | 76 | 2016 |
| Adaptive error control for NoC switch-to-switch links in a variable noise environment Q Yu, P Ampadu 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI …, 2008 | 58 | 2008 |
| Transient and permanent error co-management method for reliable networks-on-chip Q Yu, P Ampadu 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 145-154, 2010 | 53 | 2010 |
| A hardened network-on-chip design using runtime hardware Trojan mitigation methods J Frey, Q Yu Integration 56, 15-31, 2017 | 52 | 2017 |
| Hardware security threats and potential countermeasures in emerging 3D ICs J Dofe, Q Yu, H Wang, E Salman Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 69-74, 2016 | 49 | 2016 |
| Exploiting error control approaches for hardware trojans on network-on-chip links Q Yu, J Frey 2013 IEEE international symposium on defect and fault tolerance in VLSI and …, 2013 | 49 | 2013 |
| Assessing CPA resistance of AES with different fault tolerance mechanisms H Pahlevanzadeh, J Dofe, Q Yu 2016 21st Asia and South Pacific design automation conference (ASP-DAC), 661-666, 2016 | 47 | 2016 |
| A comprehensive FPGA-based assessment on fault-resistant AES against correlation power analysis attack J Dofe, H Pahlevanzadeh, Q Yu Journal of Electronic Testing 32, 611-624, 2016 | 46 | 2016 |
| Dual-layer adaptive error control for network-on-chip links Q Yu, P Ampadu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (7 …, 2011 | 43 | 2011 |
| Security threats in approximate computing systems P Yellu, N Boskov, MA Kinsy, Q Yu Proceedings of the 2019 on Great Lakes Symposium on VLSI, 387-392, 2019 | 41 | 2019 |
| Adaptive error control for nanometer scale network-on-chip links Q Yu, P Ampadu IET computers & digital techniques 3 (6), 643-659, 2009 | 39 | 2009 |
| Thwarting security threats from malicious FPGA tools with novel FPGA-oriented moving target defense Z Zhang, L Njilla, CA Kamhoua, Q Yu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (3), 665-678, 2018 | 33 | 2018 |
| Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration Q Yu, M Zhang, P Ampadu Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on …, 2011 | 33 | 2011 |
| A flexible parallel simulator for networks-on-chip with error control Q Yu, P Ampadu ieee transactions on computer-aided design of integrated circuits and …, 2009 | 33 | 2009 |
| Exploiting state obfuscation to detect hardware trojans in NoC network interfaces J Frey, Q Yu 2015 IEEE 58th International Midwest Symposium on Circuits and Systems …, 2015 | 31 | 2015 |
| Hardware-efficient logic camouflaging for monolithic 3-D ICs C Yan, J Dofe, S Kontak, Q Yu, E Salman IEEE Transactions on Circuits and Systems II: Express Briefs 65 (6), 799-803, 2017 | 29 | 2017 |
| A dual-layer method for transient and permanent error co-management in noc links Q Yu, P Ampadu IEEE Transactions on Circuits and Systems II: Express Briefs 58 (1), 36-40, 2010 | 27 | 2010 |
| Exploiting hardware obfuscation methods to prevent and detect hardware trojans Q Yu, J Dofe, Z Zhang 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 26 | 2017 |
| Error control integration scheme for reliable NoC Q Yu, B Zhang, Y Li, P Ampadu Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 26 | 2010 |
