Mojtaba Valinataj
Cited by
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A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip
M Valinataj, S Mohammadi, J Plosila, P Liljeberg, H Tenhunen
AEU-International Journal of Electronics and Communications 65 (7), 630-640, 2011
A fault-tolerant and congestion-aware routing algorithm for networks-on-chip
M Valinataj, S Mohammadi, J Plosila, P Liljeberg
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010
Novel low-cost and fault-tolerant reversible logic adders
M Valinataj, M Mirshekar, H Jazayeri
Computers & Electrical Engineering 53, 56-72, 2016
Fault tolerant arithmetic operations with multiple error detection and correction
M Valinataj, S Safari
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors
M Valinataj
Microelectronics Reliability 55 (12), 2845-2857, 2015
Fault-aware and reconfigurable routing algorithms for Networks-on-Chip
M Valinataj, S Mohammadi, S Safari
IETE Journal of Research 57 (3), 215-223, 2011
A novel self-checking carry lookahead adder with multiple error detection/correction
M Valinataj
Microprocessors and Microsystems 38 (8), 1072-1081, 2014
A low-cost high-speed self-checking carry select adder with multiple-fault detection
M Valinataj, A Mohammadnezhad, J Nurmi
Microelectronics Journal 81, 16-27, 2018
Novel parity-preserving reversible logic array multipliers
M Valinataj
The Journal of Supercomputing 73 (11), 4843-4867, 2017
Evaluation of fault-tolerant routing methods for NoC architectures
M Valinataj
2011 14th Euromicro Conference on Digital System Design, 446-449, 2011
Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents
M Valinataj, P Liljeberg, J Plosila
2013 IEEE 16th International Symposium on Design and Diagnostics of …, 2013
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications
M Valinataj, S Mohammadi
2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 13-18, 2010
A multi-start path-relinking algorithm for the flexible job-shop scheduling problem
S Bakhtar, H Jazayeriy, M Valinataj
2015 7th Conference on Information and Knowledge Technology (IKT), 1-6, 2015
Enhanced multiple-error resilient carry look-ahead adders through new customized fault-tolerant voters
M Valinataj
Microelectronics Reliability 96, 7-20, 2019
A fault-tolerant and hierarchical routing algorithm for NoC architectures
M Valinataj, P Liljeberg, J Plosila
2011 NORCHIP, 1-6, 2011
A link failure aware routing algorithm for Networks-on-Chip in nano technologies
M Valinataj, S Mohammadi, S Safari, J Plosila
2009 9th IEEE Conference on Nanotechnology (IEEE-NANO), 687-690, 2009
Reliability improvement of fault-tolerant shuffle exchange interconnection networks
R Gholizadeh, M Valinataj
2020 10th International Conference on Computer and Knowledge Engineering …, 2020
A novel area-delay efficient carry select adder based on new add-one circuit
MA Roodposhti, M Valinataj
2019 9th International Conference on Computer and Knowledge Engineering …, 2019
Reliability and performance evaluation of fault-aware routing methods for network-on-chip architectures
M Valinataj
International Journal of Engineering 27 (4), 509-516, 2014
Reliable on-chip network design using an agent-based management method
M Valinataj, P Liljeberg, J Plosila
Proceedings of the 19th International Conference Mixed Design of Integrated …, 2012
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