Follow
Andrew Hilton
Andrew Hilton
Verified email at ee.duke.edu - Homepage
Title
Cited by
Cited by
Year
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes
M Comparan, AD Hilton, HM Jacobson, BM Rogers, RA Shearer, KV Vu, ...
US Patent 9,354,884, 2016
742016
iCFP: Tolerating all-level cache misses in in-order processors
A Hilton, S Nagarakatte, A Roth
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
732009
PoisonIvy: Safe speculation for secure memory
TS Lehman, AD Hilton, BC Lee
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
682016
Global branch prediction using branch and fetch group history
TH Heil, AD Hilton
US Patent 9,921,846, 2018
522018
BOLT: Energy-efficient out-of-order latency-tolerant execution
A Hilton, A Roth
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
402010
Ginger: Control independence using tag rewriting
AD Hilton, A Roth
ACM SIGARCH Computer Architecture News 35 (2), 436-447, 2007
372007
FIESTA: A sample-balanced multi-program workload methodology
A Hilton, N Eswaran, A Roth
Proc. MoBS, 2009
352009
Load latency speculation in an out-of-order computer processor
TH Heil, AD Hilton, AJ Muff
US Patent 9,256,428, 2016
332016
Xchange: coupling parallel applications in a dynamic environment
H Abbasi, M Wolf, K Schwan, G Eisenhauer, A Hilton
2004 IEEE International Conference on Cluster Computing (IEEE Cat. No …, 2004
292004
Maps: Understanding metadata access patterns in secure memory
TS Lehman, AD Hilton, BC Lee
2018 IEEE international symposium on performance analysis of systems and …, 2018
192018
Load latency speculation in an out-of-order computer processor
TH Heil, AD Hilton, AJ Muff
US Patent 9,262,160, 2016
182016
CPROB: Checkpoint processing with opportunistic minimal recovery
A Hilton, N Eswaran, A Roth
2009 18th International Conference on Parallel Architectures and Compilation …, 2009
152009
Translation from problem to code in seven steps
AD Hilton, GM Lipp, SH Rodger
Proceedings of the ACM Conference on Global Computing Education, 78-84, 2019
132019
Flexible register management using reference counting
S Battle, AD Hilton, M Hempstead, A Roth
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
132012
Decoupled store completion/silent deterministic replay: Enabling scalable data memory for CPR/CFP processors
A Hilton, A Roth
ACM SIGARCH Computer Architecture News 37 (3), 245-254, 2009
132009
Multi-program benchmark definition
AN Jacobvitz, AD Hilton, DJ Sorin
2015 IEEE international symposium on performance analysis of systems and …, 2015
122015
DynaSprint: Microarchitectural sprints with dynamic utility and thermal management
Z Huang, JA Joao, A Rico, AD Hilton, BC Lee
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
92019
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes
M Comparan, AD Hilton, HM Jacobson, BM Rogers, RA Shearer, KV Vu, ...
US Patent 10,831,504, 2020
52020
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes
M Comparan, AD Hilton, HM Jacobson, BM Rogers, RA Shearer, KV Vu, ...
US Patent 10,114,652, 2018
52018
SMT-directory: Efficient load-load ordering for SMT
A Hilton, A Roth
IEEE Computer Architecture Letters 9 (1), 25-28, 2010
52010
The system can't perform the operation now. Try again later.
Articles 1–20