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Juergen Koehl
Juergen Koehl
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Verified email at akoehl.com - Homepage
Title
Cited by
Cited by
Year
Use of redundant routes to increase the yield and reliability of a VLSI layout
MT Buehler, JM Cohn, DJ Hathaway, JD Hibbeler, J Koehl
US Patent 7,308,669, 2007
2102007
An analytic net weighting approach for performance optimization in circuit placement
RS Tsay, J Koehl
Proceedings of the 28th ACM/IEEE Design Automation Conference, 620-625, 1991
1071991
Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk
A Hetzel, E Klink, J Koehl, D Wendel, PT Patel
US Patent 6,218,631, 2001
772001
DFM/DFY design for manufacturability and yield-influence of process variations in digital, analog and mixed-signal circuit design
M Bühler, J Koehl, J Bickford, J Hibbeler, U Schlichtmann, R Sommer, ...
Proceedings of the conference on Design, automation and test in Europe …, 2006
70*2006
Analysis, reduction and avoidance of crosstalk on VLSI chips
T Stöhr, M Alt, A Hetzel, J Koehl
Proceedings of the 1998 international symposium on Physical design, 211-218, 1998
631998
Formal verification made easy
T Schlipf, T Buechner, R Fritz, M Helms, J Koehl
IBM Journal of Research and Development 41 (4.5), 567-576, 1997
461997
DFM/DFY design for manufacturability and yield-influence of process variations in digital, analog and mixed-signal circuit design
M Bühler, J Koehl, J Bickford, J Hibbeler, U Schlichtmann, R Sommer, ...
Proceedings of the conference on Design, automation and test in Europe …, 2006
422006
Switching arrangement and method with separated output buffers
RP Luijten, C Minkenberg, N Schumacher, J Koehl, B Leppla
US Patent 7,145,873, 2006
332006
Yield improvement by local wiring redundancy
J Bickford, M Buhler, J Hibbeler, J Koehl, D Muller, S Peyer, C Schulte
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-478, 2006
292006
Designing mega-ASICs in nanogate technologies
DE Lackey, PS Zuchowski, J Koehl
Proceedings of the 40th annual Design Automation Conference, 770-775, 2003
252003
Method and apparatus for enabling parallel layout checking of designing VLSI-chips
H Folberth, J Keinert, J Koehl, K Pollmann, O Rettig
US Patent 6,237,128, 2001
192001
METHOD AND APPARATUS FOR ENABLING PARALLEL LAYOUT CHECKING OF DESIGNING VLSI-CHIPS
HFJKJKKPO Rettig
US Patent 6,237,128, 0
19
IBM's 50 million gate ASICs
J Koehl, DE Lackey, G Doerre
Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003
172003
Method for routing data paths in a semiconductor chip with a plurality of layers
A Arp, J Koehl, M Ringe
US Patent 7,526,743, 2009
162009
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
BA Anderson, JP Bickford, M Buehler, JD Hibbeler, J Koehl, EJ Nowak
US Patent 8,234,594, 2012
142012
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
BA Anderson, JP Bickford, M Buehler, JD Hibbeler, J Koehl, EJ Nowak
US Patent 8,234,594, 2012
142012
A flat, timing-driven design system for a high-performance CMOS processor chipset
J Koehl, U Baur, T Ludwig, B Kick, T Pflueger
Proceedings Design, Automation and Test in Europe, 312-320, 1998
141998
Method and system for placing logic nodes based on an estimated wiring congestion
U Brenner, PS Honsinger, J Koehl, B Korte, A Rohe, JP Vygen
US Patent 6,904,584, 2005
132005
Robust wiring networks for DfY considering timing constraints
PV Panitz, M Olbrich, E Barke, J Koehl
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 43-48, 2007
122007
Robust wiring networks for DfY considering timing constraints
PV Panitz, M Olbrich, E Barke, J Koehl
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 43-48, 2007
122007
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