David A. Wood

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Mark D. HillUniversity of Wisconsin-Madison Professor EmeritusVerified email at cs.wisc.edu
Steven K. ReinhardtMicrosoftVerified email at microsoft.com
Daniel J. SorinProfessor of ECE and Computer Science, Duke UniversityVerified email at ee.duke.edu
James R LarusProfessor Emeritus, EPFLVerified email at larusstone.org
Somayeh SardashtiUniversity of Wisconsin-MadisonVerified email at cs.wisc.edu
Milo M. K. MartinGoogle (Former Associate Professor, University of Pennsylvania)Verified email at google.com
Rathijit SenMicrosoft Gray Systems LabVerified email at microsoft.com
Derek HowerQualcommVerified email at cs.wisc.edu
Babak FalsafiProfessor of Computer Science, EPFLVerified email at epfl.ch
Alaa R. AlameldeenSimon Fraser UniversityVerified email at cs.sfu.ca
Randy KatzUniversity of California, BerkeleyVerified email at cs.Berkeley.edu
Alvin R. LebeckProfessor Computer Science and Electrical and Computer Engineering, Duke UniversityVerified email at cs.duke.edu
Joel HestnessPrincipal Research Scientist, Cerebras SystemsVerified email at cs.wisc.edu
Jayaram BobbaIntel CorporationVerified email at intel.com
Muhammad Shoaib Bin AltafOracle CorpVerified email at oracle.com
Nilay VaishGoogleVerified email at google.com
Michael R. MartyGoogleVerified email at google.com
Michael SwiftProfessor of Computer Science, University of Wisconsin--MadisonVerified email at cs.wisc.edu
Arkaprava BasuAssociate Professor at Indian Institute of Science (IISc)Verified email at iisc.ac.in
Tushar KrishnaAssociate Professor, Georgia TechVerified email at ece.gatech.edu

David A. Wood

University of Wisconsin, Madison

Verified email at cs.wisc.edu - Homepage

Computer architecture


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The gem5 simulator N Binkert, B Beckmann, G Black, SK Reinhardt, A Saidi, A Basu, ... ACM SIGARCH computer architecture news 39 (2), 1-7, 2011	6254	2011
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset MMK Martin, DJ Sorin, BM Beckmann, MR Marty, M Xu, AR Alameldeen, ... ACM SIGARCH Computer Architecture News 33 (4), 92-99, 2005	2129	2005
Implementation techniques for main memory database systems DJ DeWitt, RH Katz, F Olken, LD Shapiro, MR Stonebraker, DA Wood ACM SIGMOD Record 14 (2), 1-8, 1984	1358	1984
LogTM: Log-based transactional memory KE Moore, J Bobba, MJ Moravan, MD Hill, DA Wood Proceedings of the 12th International Symposium on High-Performance Computer …, 2006	977	2006
DBMSs on a modern processor: Where does time go? A Ailamaki, DJ DeWitt, MD Hill, DA Wood Proceedings of the International Conference on Very Large Data Bases, 266-277, 1999	772	1999
Tempest and Typhoon: User-level shared memory SK Reinhardt, JR Larus, DA Wood Proceedings of the 21st annual international symposium on Computer …, 1994	556	1994
A primer on memory consistency and cache coherence D Sorin, M Hill, D Wood Springer Nature, 2022	526	2022
The wisconsin wind tunnel: Virtual prototyping of parallel computers SK Reinhardt, MD Hill, JR Larus, AR Lebeck, JC Lewis, DA Wood Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and …, 1993	526	1993
Managing wire delay in large chip-multiprocessor caches BM Beckmann, DA Wood 37th International Symposium on Microarchitecture (MICRO-37'04), 319-330, 2004	502	2004
LogTM-SE: Decoupling hardware transactional memory from caches L Yen, J Bobba, MR Marty, KE Moore, H Volos, MD Hill, MM Swift, ... 2007 IEEE 13th International Symposium on High Performance Computer …, 2007	475	2007
Adaptive cache compression for high-performance processors AR Alameldeen, DA Wood ACM SIGARCH Computer Architecture News 32 (2), 212, 2004	441	2004
SafetyNet: Improving the availability of shared memory multiprocessors with global checkpoint/recovery DJ Sorin, MMK Martin, MD Hill, DA Wood ACM SIGARCH Computer Architecture News 30 (2), 123-134, 2002	430	2002
Token coherence: Decoupling performance and correctness MMK Martin, MD Hill, DA Wood ACM SIGARCH Computer Architecture News 31 (2), 182-193, 2003	425	2003
Implementing a cache consistency protocol RH Katz, SJ Eggers, DA Wood, CL Perkins, RG Sheldon ACM SIGARCH Computer Architecture News 13 (3), 276-283, 1985	423	1985
Fine-grain access control for distributed shared memory I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood Proceedings of the sixth international conference on Architectural support …, 1994	394	1994
Frequent pattern compression: A significance-based compression scheme for L2 caches AR Alameldeen, DA Wood Dept. of Computer Sciences, University of Wisconsin-Madison, Tech. Rep, 2004	368	2004
Variability in architectural simulations of multi-threaded workloads AR Alameldeen, DA Wood The Ninth International Symposium on High-Performance Computer Architecture …, 2003	362	2003
Cache profiling and the SPEC benchmarks: A case study AR Lebeck, DA Wood Computer 27 (10), 15-26, 1994	344	1994
gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, MS Orr, MD Hill, DA Wood IEEE Computer Architecture Letters 14 (1), 34-36, 2014	338	2014
The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020	330	2020

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