| Goldmine: Automatic assertion generation using data mining and static analysis S Vasudevan, D Sheridan, S Patel, D Tcheng, B Tuohy, D Johnson 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 189 | 2010 |
| Mining hardware assertions with guidance from static analysis S Hertz, D Sheridan, S Vasudevan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 105 | 2013 |
| Efficient validation input generation in RTL by hybridized source code analysis L Liu, S Vasudevan 2011 Design, Automation & Test in Europe, 1-6, 2011 | 90 | 2011 |
| Integration of data mining and static analysis for hardware design verification S Vasudevan, D Sheridan, L Liu US Patent 9,021,409, 2015 | 79 | 2015 |
| Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor S Gurumurthy, S Vasudevan, JA Abraham 2006 IEEE International Test Conference, 1-9, 2006 | 74 | 2006 |
| Automated mapping of pre-computed module-level test sequences to processor instructions S Guramurthy, S Vasudevan, JA Abraham IEEE International Conference on Test, 2005., 10 pp.-303, 2005 | 65 | 2005 |
| Automatic verification of arithmetic circuits in RTL using stepwise refinement of term rewriting systems S Vasudevan, V Viswanath, RW Sumners, JA Abraham IEEE Transactions on Computers 56 (10), 1401-1414, 2007 | 51 | 2007 |
| Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection S Ma, D Pal, R Jiang, S Ray, S Vasudevan 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2015 | 50 | 2015 |
| STAR: Generating input vectors for design validation by static analysis of RTL L Liu, S Vasudevan 2009 IEEE International High Level Design Validation and Test Workshop, 32-37, 2009 | 48 | 2009 |
| Automatic decomposition for sequential equivalence checking of system level and RTL descriptions S Vasudevan, JA Abraham, V Viswanath, J Tu Fourth ACM and IEEE International Conference on Formal Methods and Models …, 2006 | 45 | 2006 |
| Word level feature discovery to enhance quality of assertion mining L Liu, CH Lin, S Vasudevan Proceedings of the International Conference on Computer-Aided Design, 210-217, 2012 | 36 | 2012 |
| Application level investigation of system-level ESD-induced soft failures S Vora, R Jiang, S Vasudevan, E Rosenbaum 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2016 | 35 | 2016 |
| A technique for test coverage closure using goldmine L Liu, D Sheridan, W Tuohy, S Vasudevan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 35 | 2012 |
| Automatic generation of assertions from system level design using data mining L Liu, D Sheridan, V Athavale, S Vasudevan Ninth ACM/IEEE International Conference on Formal Methods and Models for …, 2011 | 35 | 2011 |
| A coverage guided mining approach for automatic generation of succinct assertions D Sheridan, L Liu, H Kim, S Vasudevan 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 28 | 2014 |
| Improved verification of hardware designs through antecedent conditioned slicing S Vasudevan, EA Emerson, JA Abraham International Journal on Software Tools for Technology Transfer 9, 89-101, 2007 | 28 | 2007 |
| Learning semantic representations to verify hardware designs S Vasudevan, WJ Jiang, D Bieber, R Singh, CR Ho, C Sutton Advances in Neural Information Processing Systems 34, 23491-23504, 2021 | 27 | 2021 |
| Scaling input stimulus generation through hybrid static and dynamic analysis of RTL L Liu, S Vasudevan ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014 | 27 | 2014 |
| Efficient model checking of hardware using conditioned slicing S Vasudevan, EA Emerson, JA Abraham Electronic Notes in Theoretical Computer Science 128 (6), 279-294, 2005 | 27 | 2005 |
| Code coverage of assertions using RTL source code analysis V Athavale, S Ma, S Hertz, S Vasudevan Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 25 | 2014 |
