| Identification of threshold functions and synthesis of threshold networks T Gowda, S Vrudhula, N Kulkarni, K Berezowski IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 61 | 2011 |
| Exploiting residue number system for power-efficient digital signal processing in embedded processors R Chokshi, KS Berezowski, A Shrivastava, SJ Piestrak Proceedings of the 2009 international conference on Compilers, architecture …, 2009 | 58 | 2009 |
| Compact binary logic circuits design using negative differential resistance devices KS Berezowski Electronics Letters 42 (16), 1, 2006 | 29 | 2006 |
| Fast and energy-efficient constant-coefficient FIR filters using residue number system P Patronik, K Berezowski, SJ Piestrak, J Biernat, A Shrivastava IEEE/ACM International Symposium on Low Power Electronics and Design, 385-390, 2011 | 28 | 2011 |
| Design of residue multipliers-accumulators using periodicity SJ Piestrak, KS Berezowski IET Irish Signals and Systems Conference (ISSC 2008), 380-385, 2008 | 28 | 2008 |
| Multiple-valued logic circuits design using negative differential resistance devices KS Berezowski, SBK Vrudhula 37th International Symposium on Multiple-Valued Logic (ISMVL'07), 24-24, 2007 | 20 | 2007 |
| Design of a robust, high performance standard cell threshold logic family for DSM technology S Leshner, N Kulkarni, S Vrudhula, K Berezowski 2010 International Conference on Microelectronics, 52-55, 2010 | 18 | 2010 |
| The landscape of wireless sensing in greenhouse monitoring and control KS Berezowski International Journal of Wireless & Mobile Networks 4 (4), 141, 2012 | 17 | 2012 |
| Architecture of efficient RNS-based digital signal processor with very low-level pipelining SJ Piestrak, KS Berezowski IET Irish Signals and Systems Conference (ISSC 2008), 127-132, 2008 | 17 | 2008 |
| Fast and accurate thermal simulation and modelling of workloads of many-core processors B Wojciechowski, KS Berezowski, P Patronik, J Biernat 2011 17th International Workshop on Thermal Investigations of ICs and …, 2011 | 13 | 2011 |
| Calibration of RO-based temperature sensors for a toolset for measuring thermal behavior of FPGA devices P Weber, M Zagrabski, B Wojciechowski, M Nikodem, K Kȩpa, ... Microelectronics Journal 45 (12), 1753-1763, 2014 | 12 | 2014 |
| Automatic design of binary and multiple-valued logic gates on RTD series KS Berezowski, SBK Vrudhula 8th Euromicro Conference on Digital System Design (DSD'05), 139-142, 2005 | 11 | 2005 |
| Toolset for measuring thermal behavior of FPGA devices P Weber, M Zagrabski, B Wojciechowski, KS Berezowski, M Nikodem, ... 19th International Workshop on Thermal Investigations of ICs and Systems …, 2013 | 9 | 2013 |
| Analytical results for design space exploration of multi-core processors employing thread migration R Rao, S Vrudhula, K Berezowski Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 9 | 2008 |
| Design of a novel flexible 4-moduli RNS and reverse converter M Wesolowski, P Patronik, K Berezowski, J Biernat IET Digital Library, 2012 | 7 | 2012 |
| Out-of-order issue logic using sorting networks SS Mhambrey, LT Clark, SK Maurya, KS Berezowski Proceedings of the 20th symposium on Great lakes symposium on VLSI, 385-388, 2010 | 7 | 2010 |
| Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis KS Berezowski Proceedings Euromicro Symposium on Digital Systems Design, 422-429, 2001 | 7 | 2001 |
| Fast and accurate thermal modeling and simulation of manycore processors and workloads B Wojciechowski, KS Berezowski, P Patronik, J Biernat Microelectronics Journal 44 (11), 986-993, 2013 | 5 | 2013 |
| Design of an RNS reverse converter for a new five-moduli special set P Patronik, KS Berezowski, J Biernat, SJ Piestrak, A Shrivastava Proceedings of the great lakes symposium on VLSI, 67-70, 2012 | 5 | 2012 |
| A low power, high performance threshold logic-based standard cell multiplier in 65 nm CMOS S Leshner, K Berezowski, X Yao, G Chalivendra, S Patel, S Vrudhula 2010 IEEE Computer Society Annual Symposium on VLSI, 210-215, 2010 | 5 | 2010 |
Stanislaw J. PiestrakProfessor of Computer Engineering, Université de Lorraine, FranceVerified email at univ-lorraine.fr
