Ioannis (Yannis) Schoinas
Ioannis (Yannis) Schoinas
Verified email at
Cited by
Cited by
Intel Virtualization Technology for Directed I/O.
D Abramson, J Jackson, S Muthrasanallur, G Neiger, G Regnier, ...
Intel technology journal 10 (3), 2006
Fine-grain access control for distributed shared memory
I Schoinas, B Falsafi, AR Lebeck, SK Reinhardt, JR Larus, DA Wood
Proceedings of the sixth international conference on Architectural support …, 1994
Application-specific protocols for user-level shared memory
B Falsafi, AR Lebeck, SK Reinhardt, I Schoinas, MD Hill, JR Larus, ...
Supercomputing'94: Proceedings of the 1994 ACM/IEEE Conference on …, 1994
Address translation for input/output devices using hierarchical translation tables
I Schoinas, R Madukkarumakumana, G Neiger, R Uhlig, K King
US Patent 7,444,493, 2008
Integration Challenges and Tradeoffs for Tera-scale Architectures.
M Azimi, N Cherukuri, DN Jayasimha, A Kumar, P Kundu, S Park, ...
Intel technology journal 11 (3), 2007
Performance enhancement of address translation using translation tables covering large address spaces
I Schoinas, G Neiger, R Madukkarumukumana, K King, R Uhlig, AR Zahir, ...
US Patent 8,843,727, 2014
Relaxed consistency and coherence granularity in DSM systems: A performance evaluation
Y Zhou, L Iftode, JP Sing, K Li, BR Toonen, I Schoinas, MD Hill, DA Wood
Proceedings of the sixth ACM SIGPLAN Symposium on Principles and Practice of …, 1997
Resource partitioning and direct access utilizing hardware support for virtualization
RS Madukkarumukumana, G Neiger, I Schoinas
US Patent 7,467,381, 2008
Interrupt redirection for virtual partitioning
RS Madukkarumukumana, I Schoinas, G Neiger
US Patent 7,222,203, 2007
Caching support for direct memory access address translation
I Schoinas, R Madukkarumukumana, G Neiger, R Uhlig, B Vembu
US Patent 7,334,107, 2008
Synchronizing memory copy operations with memory accesses
S Ramakrishnan, I Schoinas
US Patent 7,127,566, 2006
Method and apparatus for managing transaction requests in a multi-node architecture
M Khare, A Kumar, I Schoinas, LP Looi
US Patent 6,971,098, 2005
Performing memory RAS operations over a point-to-point interconnect
S Ramakrishnan, I Schoinas
US Patent 7,127,567, 2006
Fault processing for direct memory access address translation
R Madukkarumukumana, I Schoinas, K King, B Vembu, G Neiger, R Uhlig
US Patent 7,340,582, 2008
Flexible event monitoring counters in multi-node processor systems and process of operating the same
IT Schoinas, AS Oztaskin
US Patent 6,347,362, 2002
Method for enforcing resource access control in computer systems
MR Sastry, IT Schoinas, DM Cermak
US Patent 8,789,170, 2014
Implementing fine-grain distributed shared memory on commodity smp workstations
I Schoinas, B Falsafi, MD Hill, JR Larus, CE Lukas, SS Mukherjee, ...
University of Wisconsin-Madison Department of Computer Sciences, 1996
Address translation mechanisms in network interfaces
I Schoinas, MD Hill
Proceedings 1998 Fourth International Symposium on High-Performance Computer …, 1998
Arbitrating memory accesses via a shared memory fabric
DF Cutter, B Fanning, R Nagarajan, JS Niell, D Bernstein, D Limaye, ...
US Patent 9,535,860, 2017
Method, apparatus, system for qualifying CPU transactions with security attributes
MR Sastry, IT Schoinas, DM Cermak
US Patent 8,959,576, 2015
The system can't perform the operation now. Try again later.
Articles 1–20