| Network on chip routing algorithms V Rantala, T Lehtonen, J Plosila Turku Centre for Computer Science, 2006 | 230 | 2006 |
| Online reconfigurable self-timed links for fault tolerant NoC T Lehtonen, P Liljeberg, J Plosila VLSI Design 2007, 2007 | 156 | 2007 |
| Self-adaptive system for addressing permanent errors in on-chip interconnects T Lehtonen, D Wolpert, P Liljeberg, J Plosila, P Ampadu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (4), 527-540, 2010 | 104 | 2010 |
| Agile methods for embedded systems development-a literature review and a mapping study M Kaisti, V Rantala, T Mujunen, S Hyrynsalmi, K Könnölä, T Mäkilä, ... EURASIP Journal on Embedded Systems 2013 (1), 1-16, 2013 | 90 | 2013 |
| Customer loyalty card and devices associated therewith T Lehtonen, J Jantti, M Nymark US Patent App. 11/071,463, 2005 | 56 | 2005 |
| Agile methods in embedded system development: Multiple-case study of three industrial cases K Könnölä, S Suomi, T Mäkilä, T Jokela, V Rantala, T Lehtonen Journal of Systems and Software 118, 134-150, 2016 | 54 | 2016 |
| Agile principles in the embedded system development M Kaisti, T Mujunen, T Mäkilä, V Rantala, T Lehtonen International Conference on Agile Software Development, 16-31, 2014 | 43 | 2014 |
| Analysis of forward error correction methods for nanoscale networks-on-chip T Lehtonen, P Liljeberg, J Plosila Proceedings of the 2nd international conference on Nano-Networks, 3, 2007 | 42 | 2007 |
| Fault tolerance analysis of NoC architectures T Lehtonen, P Liljeberg, J Plosila 2007 IEEE International Symposium on Circuits and Systems, 361-364, 2007 | 42 | 2007 |
| On fault tolerance techniques towards nanoscale circuits and systems T Lehtonen, J Plosila, J Isoaho Turku Centre for Computer Science, 2005 | 37 | 2005 |
| Augmented reality-Towards an ethical fantasy? OI Heimo, KK Kimppa, S Helle, T Korkalainen, T Lehtonen Ethics in Science, Technology and Engineering, 2014 IEEE International …, 2014 | 30 | 2014 |
| Sulautettujen järjestelmien ketterä käsikirja T Lehtonen, S Tuomivaara, V Rantala, M Känsälä, T Mäkilä, T Jokela, ... University of Turku, 2014 | 28 | 2014 |
| High-performance long NoC link using delay-insensitive current-mode signaling E Nigussie, T Lehtonen, S Tuuna, J Plosila, J Isoaho VLSI design 2007, 2007 | 25 | 2007 |
| Multi network interface architectures for fault tolerant Network-on-Chip V Rantala, T Lehtonen, P Liljeberg, J Plosila Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on, 1-4, 2009 | 23 | 2009 |
| On fault tolerance methods for networks-on-chip T Lehtonen TUCS Dissertations 122, 2009 | 20 | 2009 |
| Examining User Experience in an Augmented Reality Adventure Game: Case Luostarinmäki Handicrafts Museum K Seppälä, OI Heimo, T Korkalainen, J Pääkylä, J Latvala, S Helle, ... IFIP International Conference on Human Choice and Computers, 257-276, 2016 | 19 | 2016 |
| Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation M Kutila, A Paasio, T Lehtonen 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 15 | 2014 |
| Fault-tolerant routing approach for reconfigurable Networks-on-Chip P Rantala, T Lehtonen, J Isoaho, J Plosila 2006 International Symposium on System-on-Chip, 1-4, 2006 | 14 | 2006 |
| Distributed Traffic Monitoring Methods for Adaptive Network-on-Chip V Rantala, T Lehtonen, P Liljeberg, J Plosila NORCHIP, 2008., 233-236, 2008 | 11 | 2008 |
| Can embedded space system development benefit from agile practices? K Könnölä, S Suomi, T Mäkilä, V Rantala, T Lehtonen EURASIP Journal on Embedded Systems 2017 (1), 3, 2017 | 10 | 2017 |
Juha PlosilaProfessor, University of Turku (UTU), FinlandVerified email at utu.fi
