Bill Lin
Cited by
Cited by
Implicit state enumeration of finite state machines using BDD's
HJ Touati, H Savoj, B Lin, RK Brayton, A Sangiovanni-Vincentelli
1990 IEEE International Conference on Computer-Aided Design. Digest of …, 1990
Synthesis of multiple-level logic from symbolic high-level description languages
B Lin
IFIP International Conference on Very Large Scale Integration, August 1989, 1989
Design environment and a design method for hardware/software co-design
K Van Rompaey, D Verkest, J Vanhoof, B Lin, I Bolsens, H De Man
US Patent 5,870,588, 1999
Power estimation methods for sequential logic circuits
CY Tsui, J Monteiro, M Pedram, S Devadas, AM Despain, B Lin
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3 (3), 404-416, 1995
Hardware/software co-design of digital telecommunication systems
I Bolsens, HJ De Man, B Lin, K Van Rompaey, S Vercauteren, D Verkest
Proceedings of the IEEE 85 (3), 391-418, 1997
A methodology for efficient estimation of switching activity in sequential logic circuits
J Monteiro, S Devadas, B Lin
Proceedings of the 31st annual Design Automation Conference, 12-17, 1994
Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines
RM Fuhrer, SM Nowick, M Theobald, NK Jha, B Lin, L Plana
Basic gate implementation of speed-independent circuits
A Kondratyev, M Kishinevsky, B Lin, P Vanbekbergen, A Yakovlev
Proceedings of the 31st annual Design Automation Conference, 56-62, 1994
Fast and scalable priority queue architecture for high-speed network switches
R Bhagwan, B Lin
Proceedings IEEE INFOCOM 2000. Conference on Computer Communications …, 2000
A generalized state assignment theory for transformations on signal transition graphs
P Vanbekbergen, B Lin, G Goossens, H De Man
Journal of VLSI signal processing systems for signal, image and video …, 1994
ORION3. 0: A comprehensive NoC router estimation tool
AB Kahng, B Lin, S Nath
IEEE Embedded Systems Letters 7 (2), 41-45, 2015
Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications
S Vercauteren, B Lin, H De Man
Proceedings of the 33rd annual Design Automation Conference, 521-526, 1996
MUSE: a multilevel symbolic encoding algorithm for state assignment
X Du, G Hachtel, B Lin, AR Newton
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1991
Design of a high-throughput distributed shared-buffer NoC router
RS Ramanujam, V Soteriou, B Lin, LS Peh
2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip, 69-78, 2010
Minimization of symbolic relations
B Lin, F Somenzi
1990 IEEE International Conference on Computer-Aided Design, 88, 89, 90, 91 …, 1990
Don't care minimization of multi-level sequential logic networks
B Lin, HJ Touati, AR Newton
1990 IEEE International Conference on Computer-Aided Design, 414,415,416,417 …, 1990
Destination-based adaptive routing on 2D mesh networks
RS Ramanujam, B Lin
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking …, 2010
Synthesis of concurrent system interface modules with automatic protocol conversion generation
B Lin, S Vercauteren
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided …, 1994
Design of application-specific 3D networks-on-chip architectures
S Yan, B Lin
3D Integration for NoC-based SoC Architectures, 167-191, 2011
A high-throughput distributed shared-buffer NoC router
V Soteriou, RS Ramanujam, B Lin, LS Peh
IEEE Computer Architecture Letters 8 (1), 21-24, 2009
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