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Roman Pletka
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Citace
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Method to efficiently locate meta-data structures on a flash-based storage device
R Haas, XY Hu, RA Pletka
US Patent 8,250,324, 2012
5102012
Write amplification analysis in flash-based solid state drives
XY Hu, E Eleftheriou, R Haas, I Iliadis, R Pletka
Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference, 1-9, 2009
4762009
Cache memory management in a flash cache architecture
ES Eleftheriou, R Haas, XY Hu, RA Pletka
US Patent 8,688,900, 2014
912014
Wear leveling of a memory array
TJ Fisher, AD Fry, N Ioannou, I Koltsidas, J Ma, RA Pletka, LT Simmons, ...
US Patent 9,857,986, 2018
832018
Cooperative data deduplication in a solid state storage array
TJ Fisher, N Ioannou, I Koltsidas, RA Pletka, S Tomic
US Patent 10,013,169, 2018
732018
Logical to physical address mapping in storage systems comprising solid state memory devices
W Bux, R Haas, XY Hu, R Pletka
US Patent 9,256,527, 2016
712016
Cryptographic security for a high-performance distributed file system
R Pletka, C Cachin
24th IEEE Conference on Mass Storage Systems and Technologies (MSST 2007 …, 2007
592007
Encryption and authentication of data and for decryption and verification of authenticity of data
C Cachin, PT Hurley, RA Pletka
US Patent App. 11/622,467, 2008
572008
Metadata hardening and parity accumulation for log-structured arrays
I Koltsidas, CJ Camp, N Ioannou, RA Pletka, AK Kourtis, S Tomic, ...
US Patent 10,437,670, 2019
552019
Reliability scheme using hybrid SSD/HDD replication with log structured management
ES Eleftheriou, R Haas, X Hu, RA Pletka
US Patent 8,700,949, 2014
532014
Bringing efficient advanced queries to distributed hash tables
D Bauer, P Hurley, R Pletka, M Waldvogel
29th Annual IEEE International Conference on Local Computer Networks, 6-14, 2004
512004
Characterization and analysis of bit errors in 3D TLC NAND flash memory
N Papandreou, H Pozidis, T Parnell, N Ioannou, R Pletka, S Tomic, ...
2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019
492019
Reducing unnecessary calibration of a memory unit for which the error count margin has been exceeded
N Ioannou, N Papandreou, RA Pletka, S Tomic
US Patent 10,824,352, 2020
472020
A comparison of secure multi-tenancy architectures for filesystem storage clouds
A Kurmus, M Gupta, R Pletka, C Cachin, R Haas
Middleware 2011: ACM/IFIP/USENIX 12th International Middleware Conference …, 2011
462011
Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory
CJ Camp, TJ Fisher, AD Fry, N Ioannou, I Koltsidas, N Papandreou, ...
US Patent 9,251,909, 2016
44*2016
Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management
CJ Camp, TJ Fisher, AD Fry, N Ioannou, R Pletka, S Tomic
US Patent 9,563,373, 2017
412017
Two-level hierarchical log structured array architecture with minimized write amplification
R Haas, N Ioannou, I Koltsidas, RA Pletka, AD Walls
US Patent 9,619,158, 2017
402017
Port scanning method and device, port scanning detection method and device, port scanning system, computer program and computer program product
RA Pletka, M Waldvogel
US Patent 8,245,298, 2012
402012
Extending useful life of a non-volatile memory by health grading
CJ Camp, I Koltsidas, N Papandreou, T Parnell, RA Pletka, C Pozidis, ...
US Patent 9,558,107, 2017
392017
Regrouping data during relocation to facilitate write amplification reduction
RS Ahmed, CJ Camp, TJ Fisher, AD Fry, N Ioannou, J Ma, MR Orr, ...
US Patent 10,884,914, 2021
382021
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