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Stephen Brown
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Field-programmable gate arrays
SD Brown, RJ Francis, J Rose, ZG Vranesic
Springer Science & Business Media, 2012
13572012
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
A Canis, J Choi, M Aldham, V Zhang, A Kammoona, JH Anderson, ...
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
8182011
Fundamentals of digital logic with Verilog design
SD Brown, ZG Vranesic
McGraw-Hill, 2003
7442003
A survey and evaluation of FPGA high-level synthesis tools
R Nane, VM Sima, C Pilato, J Choi, B Fort, A Canis, YT Chen, H Hsiao, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
7402015
FPGA and CPLD architectures: A tutorial
S Brown, J Rose
IEEE design & test of computers 13 (2), 42-57, 1996
4881996
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
A Canis, J Choi, M Aldham, V Zhang, A Kammoona, T Czajkowski, ...
ACM Transactions on Embedded Computing Systems (TECS) 13 (2), 1-27, 2013
4772013
Fundamentals of digital logic with VHDL design
SD Brown, ZG Vranesic
McGraw-Hill, 2000
4222000
Architecture of FPGAs and CPLDs: A tutorial
S Brown, J Rose
IEEE Design and Test of Computers 13 (2), 42-57, 1996
3891996
Flexibility of interconnection structures for field-programmable gate arrays
J Rose, S Brown
IEEE Journal of Solid-State Circuits 26 (3), 277-282, 1991
3231991
A detailed router for field-programmable gate arrays
S Brown, J Rose, ZG Vranesic
IEEE transactions on computer-aided design of integrated circuits and …, 1992
2451992
A detailed routing algorithm for allocating wire segments in field-programmable gate arrays
GG Lemieux, SD Brown
Proc. ACM/SIGDA Physical Design Workshop, Lake Arrowhead, CA, 215-226, 1993
1921993
Post-publication sharing of data and tools
PN Schofield, T Bubela, T Weaver, L Portilla, SD Brown, JM Hancock, ...
Nature 461 (7261), 171-173, 2009
1812009
Hybrid FPGA architecture
A Kaviani, S Brown
Proceedings of the 1996 ACM fourth international symposium on Field …, 1996
1701996
Heuristics for area minimization in LUT-based FPGA technology mapping
V Manohararajah, SD Brown, ZG Vranesic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
1602006
Computational field programmable architecture
A Kaviani, D Vranesic, S Brown
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No …, 1998
1321998
Modulo SDC scheduling with recurrence minimization in high-level synthesis
A Canis, SD Brown, JH Anderson
2014 24th International Conference on Field Programmable Logic and …, 2014
1052014
From software threads to parallel hardware in high-level synthesis for FPGAs
J Choi, S Brown, J Anderson
2013 International Conference on Field-Programmable Technology (FPT), 270-277, 2013
1052013
Programmable logic device configured to accommodate multiplication
BB Pedersen, S Shumarayev, WJ Huang, V Chan, S Brown, T Ngai, ...
US Patent 6,323,680, 2001
1052001
FPGA architectural research: a survey
S Brown
IEEE Design & Test of Computers 13 (4), 9-15, 1996
1051996
FPGA technology mapping: a study of optimality
A Ling, DP Singh, SD Brown
Proceedings of the 42nd annual Design Automation Conference, 427-432, 2005
982005
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