Pekka Jääskeläinen
Pekka Jääskeläinen
Associate Professor in Tampere University, Principal Engineer in Intel
Verified email at - Homepage
Cited by
Cited by
pocl: A performance-portable opencl implementation
P Jääskeläinen, CS de La Lama, E Schnetter, K Raiskila, J Takala, ...
International Journal of Parallel Programming 43 (5), 752-785, 2015
OpenCL-based design methodology for application-specific processors
PO Jäskeläinen, CS de La Lama, P Huerta, JH Takala
2010 International Conference on Embedded Computer Systems: Architectures …, 2010
Customized exposed datapath soft-core design flow with compiler support
O Esko, P Jääskeläinen, P Huerta, CS de La Lama, J Takala, JI Martinez
Field Programmable Logic and Applications (FPL), 2010 International …, 2010
Codesign toolset for application-specific instruction-set processors
P Jääskeläinen, V Guzma, A Cilio, T Pitkänen, J Takala
Electronic Imaging 2007, 65070X-65070X-11, 2007
Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction
M Koskela, K Immonen, M Mäkitalo, A Foi, T Viitanen, P Jääskeläinen, ...
ACM Transactions on Graphics (TOG) 38 (5), 1-14, 2019
HW/SW Co-design Toolset for Customization of Exposed Datapath Processors
P Jääskeläinen, T Viitanen, J Takala, H Berg
Computing Platforms for Software-Defined Radio, 147-164, 2017
Code density and energy efficiency of exposed datapath architectures
P Jääskeläinen, H Kultala, T Viitanen, J Takala
Journal of Signal Processing Systems 80 (1), 49-64, 2015
The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems
Z Al-Ars, T Basten, A de Beer, M Geilen, D Goswami, P Jääskeläinen, ...
Proceedings of the 16th ACM International Conference on Computing Frontiers …, 2019
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs
H Yviquel, A Sanchez, P Jääskeläinen, J Takala, M Raulet, E Casseau
Journal of Signal Processing Systems 80 (1), 121-136, 2015
Transport-Triggered Soft Cores
P Jääskeläinen, A Tervo, G Payá Vayá, T Viitanen, N Behmann, J Takala, ...
RAW: 25th Anniversary of Reconfigurable Architectures Workshop, 2018
Impact of software bypassing on instruction level parallelism and register file traffic
V Guzma, P Jääskeläinen, P Kellomäki, J Takala
Embedded Computer Systems: Architectures, Modeling, and Simulation, 23-32, 2008
Grover: looking for performance improvement by disabling local memory usage in OpenCL kernels
J Fang, H Sips, P Jaaskelainen, AL Varbanescu
Parallel Processing (ICPP), 2014 43rd International Conference on, 162-171, 2014
Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms
H Yviquel, E Casseau, M Raulet, P Jääskeläinen, J Takala
2013 8th International Symposium on Image and Signal Processing and Analysis …, 2013
Foveated Real-Time Path Tracing in Visual-Polar Space
M Koskela, A Lotvonen, M Mäkitalo, P Kivi, T Viitanen, P Jääskeläinen
Proceedings of 30th Eurographics Symposium on Rendering, 2019
HIPCL: Tool for Porting CUDA Applications to Advanced OpenCL Platforms Through HIP
M Babej, P Jääskeläinen
Proceedings of the International Workshop on OpenCL, 1-3, 2020
Foveated Path Tracing
M Koskela, T Viitanen, P Jääskeläinen, J Takala
International Symposium on Visual Computing, 723-732, 2016
Low-power application-specific FFT processor for LTE applications
T Patyk, D Guevorkian, T Pitkänen, P Jääskeläinen, J Takala
2013 International Conference on Embedded Computer Systems: Architectures …, 2013
A 122Mb/s Turbo decoder using a mid-range GPU
J Xianjun, C Canfeng, P Jääskeläinen, V Guzma, H Berg
2013 9th International Wireless Communications and Mobile Computing …, 2013
Simplified floating-point division and square root
T Viitanen, P Jääskeläinen, O Esko, J Takala
2013 IEEE International Conference on Acoustics, Speech and Signal …, 2013
Instruction set simulator for transport triggered architectures
P Jääskeläinen
Master's thesis, Department of Information Technology, Tampere University of …, 2005
The system can't perform the operation now. Try again later.
Articles 1–20