Albert Meixner
Albert Meixner
Unknown affiliation
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Cited by
Cited by
Argus: Low-cost, comprehensive error detection in simple cores
A Meixner, ME Bauer, D Sorin
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
Architectures for online error detection and recovery in multicore processors
D Gizopoulos, M Psarakis, SV Adve, P Ramachandran, SKS Hari, D Sorin, ...
2011 Design, Automation & Test in Europe, 1-6, 2011
Variable fragment shading with surface recasting
EB Lum, RL Dimitrov, IL Ubieto, PJ Neill, Y Uralsky, A Meixner
US Patent 9,355,483, 2016
Dynamic verification of memory consistency in cache-coherent multithreaded computer architectures
A Meixner, DJ Sorin
IEEE Transactions on Dependable and Secure Computing 6 (1), 18-31, 2008
Detouring: Translating software to circumvent hard faults in simple cores
A Meixner, DJ Sorin
2008 IEEE International Conference on Dependable Systems and Networks With …, 2008
Error detection using dynamic dataflow verification
A Meixner, DJ Sorin
16th International Conference on Parallel Architecture and Compilation …, 2007
Virtual linebuffers for image signal processors
Q Zhu, O Shacham, JR Redgrave, DF Finchelstein, A Meixner
US Patent 9,749,548, 2017
Dynamic verification of sequential consistency
A Meixner, DJ Sorin
32nd International Symposium on Computer Architecture (ISCA'05), 482-493, 2005
Architecture for high performance, power efficient, programmable image processing
Q Zhu, O Shacham, A Meixner, JR Redgrave, DF Finchelstein, ...
US Patent 9,965,824, 2018
Error detection via online checking of cache coherence with token coherence signatures
A Meixner, DJ Sorin
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
Convolutional neural network on programmable two dimensional image processor
O Shacham, D Patterson, WR Mark, A Meixner, DF Finchelstein, ...
US Patent 10,546,211, 2020
Line buffer unit for image processor
N Desai, A Meixner, Q Zhu, JR Redgrave, O Shacham, DF Finchelstein
US Patent 9,756,268, 2017
Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
A Meixner
US Patent 9,785,423, 2017
Two dimensional shift array for image processor
O Shacham, JR Redgrave, A Meixner, Q Zhu, DF Finchelstein, ...
US Patent 9,769,356, 2017
Sheet generator for image processor
A Meixner, JR Redgrave, O Shacham, Q Zhu, DF Finchelstein
US Patent 10,291,813, 2019
Energy efficient processor core architecture for image processor
A Meixner, JR Redgrave, O Shacham, DF Finchelstein, Q Zhu
US Patent 9,772,852, 2017
Lazy error detection for microprocessor functional units
M Yilmaz, A Meixner, S Ozev, DJ Sorin
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007
Pixel visual core: Google’s fully programmable image vision and AI processor for mobile devices
J Redgrave, A Meixner, N Goulding-Hotta, A Vasilyev, O Shacham
Proc. IEEE Hot Chips Symp.(HCS), 1-18, 2018
Analysis of a wavelet-based robust hash algorithm
A Meixner, A Uhl
Security, Steganography, and Watermarking of Multimedia Contents VI 5306 …, 2004
Tile shader for screen space, a method of rendering and a graphics processing unit employing the tile shader
A Meixner
US Patent 9,224,227, 2015
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